This invention relates generally to output buffer circuits and more particularly, it relates to an ECL output buffer circuit which provides a stable predetermined output voltage swing over power supply, temperature and process variations but yet has a high speed of operation with low power consumption.
As is generally known in the art of output buffer circuits, it is generally desirable to maintain accurately the D.C. output voltage level V.sub.OH corresponding to the high logic level and the D.C. voltage output level V.sub.OL corresponding to the low logic level in order to achieve high operating speeds, adequate noise margins and low power consumption and to prevent the output voltages from being affected by variations in process, power supply voltages, and temperature. In particular, this is especially important so as to avoid saturation of the internal transistors when designing the output levels for a "lower-than-low" operation, i.e., where the output level is lower than the normal low logic level V.sub.OL. Therefore, there is generally required some sort of compensation circuit to produce a compensating current I.sub.COMP in order to make the output voltages independent of supply-voltage variations and temperature variations.
In FIG. 1, there is shown an ECL output buffer circuit of the prior art which includes a compensation circuit to provide a compensating current I.sub.COMP for the output voltage level V.sub.OH. The values of compensating current I.sub.COMP varies over the temperature range. Since the values of the compensating current I.sub.COMP are a definite function of the temperature coefficients of the resistors R1, R10, R9, R8; the transistors Q3, Q4; and the gate current I.sub.G, and further since the temperature coefficients of the resistors and transistors are fixed by process, then a predetermined output voltage level V.sub.OH or V.sub.OL can be obtained only by changing the gate current I.sub.G. With this compensation scheme, a very high gate current I.sub.G is required and thus causing higher power consumption. Further, due to the close relationship of the compensating current I.sub.COMP and the gate current I.sub.G this makes the design very difficult and greatly dependent on process tolerances. It would therefore be desirable to provide an improved ECL output buffer circuit which provides a stable predetermined output voltage swing over power supply, temperature and process variation.